Logic Gates
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These elements would reside in a new category, entitled “Logic”. This category would have a symbol representing binary numbers.
NOTE: INST w/ set .TMP is only used for inputs and outputs because it would be easier to integrate with other electronics. Only the pixel in contact with the logic gate needs to have a .TMP set.
AND (AND Gate):
Color - rgb(196, 201, 139)
Description - “AND Gate, outputs when both inputs are SPRK'd.”
Properties -
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INST with a .TMP of 1 and 2 are inputs.
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INST with a .TMP of 3 is the output.
NOT (NOT Gate):
Color - rgb(196, 201, 139)
Description - “NOT Gate, outputs when the input isn’t SPRK’d.”
Properties -
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INST with a .TMP of 1 is the input.
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INST with a .TMP of 2 is the output.
OR (OR Gate):
Color - rgb(196, 201, 139)
Description - “OR Gate, outputs when either input is SPRK’d.”
Properties -
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INST with a .TMP of 1 and 2 are the inputs.
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INST with a .TMP of 3 is the output.
XOR (XOR Gate):
Color - rgb(196, 201, 139)
Description - “XOR Gate, outputs when either input is SPRK’d, but not when both are SPRK’d.”
Properties -
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INST with a .TMP of 1 and 2 are the inputs.
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INST with a .TMP of 3 is the output.
NAND (NAND Gate):
Color - rgb(196, 201, 139)
Description - “NAND Gate, does not output when both inputs are SPRK’d.”
Properties -
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INST with a .TMP of 1 and 2 are the inputs.
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INST with a .TMP of 3 is the output.
NOR (NOR Gate):
Color - rgb(196, 201, 139)
Description - “NOR Gate, does not output when either output is SPRK’d.”
Properties -
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INST with a .TMP of 1 and 2 are the inputs.
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INST with a .TMP of 3 is the output.
XNOR (XNOR Gate):
Color - rgb(196, 201, 139)
Description - “XNOR Gate, does not output when either input is SPRK’d, but not when both are SPRK’d.”
Properties -
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INST with a .TMP of 1 and 2 are the inputs.
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INST with a .TMP of 3 is the output.
FFLP (Flip-Flop, namely a T flip-flop):
Color - rgb(196, 201, 139)
Description - “T-Flip Flop, Toggles when the input is SPRK’d.”
Properties -
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INST with a .TMP of 1 is T.
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INST with a .TMP of 2 is CLOCK.
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INST with a .TMP of 3 is Q.
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INST with a .TMP of 4 is Q’.
LTCH (Latch, namely a SR Latch):
Color - rgb(196, 201, 139)
Description - “SR Latch, toggles between outputs when set and reset are SPRK’d.”
Properties -
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INST with a .TMP of 1 is S.
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INST with a .TMP of 2 is R.
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INST with a .TMP of 3 is Q.
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INST with a .TMP of 4 is Q’.
Use Cases:
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More compact electronics. Instead of making your own logic gates, these logic gates would just be a single pixel!
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Faster response times/More reliable gates. Regular logic gates made in TPT (excluding subframe, but that’s complicated to use) can be slow to react, and can even fail to work properly.
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Friendlier entrance to electronics. Instead of needing to use weird elements (NTCT? PTCT? NSCN? PSCN?, NOTE: I ACTUALLY KNOW WHAT THESE ARE), why not use logic gates?
Edited once by Fusionftw. Last: 28th May 2020 -
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This post is hidden because the user is banned
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I honestly think it's more user-friendly to just set the .tmp of a FILT particle, and voila you have a 29-bit AND, OR, NOT, whatever gate. And the code for these logic gates would be complex (managing timing), plus the need to add a whole bunch of new elements. The costs very much outweigh the benefits imo. But in the end, it is up to the devs
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It's meant to be beginner friendly.
Also, wouldn't it be easy to code (i'm not sure about the flipflop/latch)?
If we're looking at the AND gate for example, can't you just do this:
Psuedocode:
input1 = check for SPRK from INST w/ a .tmp of 1
input2 = check for SPRK from INST w/ a .tmp of 2
if( input1 && input2 ) = true {
SPRK all INST w/ a .tmp of 3 touching the AND element
}
Edited once by Fusionftw. Last: 2nd Jun 2020 -
Bumping this.
Also, this suggestion would make it easier to build computers.
More Elements:
FADD (Full Adder):
Color - rgb(196, 201, 139)
Description - “Full Adder, adds 2 bits.”
Properties -
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INST with a .TMP of 1 is A.
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INST with a .TMP of 2 is B.
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INST with a .TMP of 3 is Cin.
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INST with a .TMP of 4 is Sum.
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INST with a .TMP of 5 is Cout.
FSUB (Full Subtractor):
Color - rgb(196, 201, 139)
Description - “Full Subtractor, subtracts 2 bits.”
Properties -
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INST with a .TMP of 1 is A.
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INST with a .TMP of 2 is B.
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INST with a .TMP of 3 is Bin.
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INST with a .TMP of 4 is Difference.
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INST with a .TMP of 5 is Bout.
Edited once by Fusionftw. Last: 3rd Jun 2020 -
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The timing would definitely be confusing. SPRK has an 8 frame cycle. 4 frames of spark, 4 frames of metal. The logic gates would also need to have the same 8 frame cycle. What if a spark comes from one side of an XOR gate one frame before it comes on the other side? Should it output a spark? Or should it wait 4 frames before deciding?
The .tmp setting is also arbitrary, nobody will really know how to do that. At least for FILT it shows in the HUD. But with this you'd have to memorize lots of .tmp settings for each logic gate type.
I also don't think there is much demand for a SPRK logic gate element. Everyone doing advanced stuff already does FILT because it is instantaneous (1 frame cycle, not 8 frames). Anyone using SPRK won't have too much trouble designing their own logic gates.
In summary, -
I forgot to add that the logic gates would actually check for SPRK every 5 frames, so that INST's SPRK cooldown wouldn't make the logic gate think that there's no signal.
I chose to use INST and set it's .TMP for these logic gates because I felt that would be the easiest way to actually input signals, because using a different element for each input/output would quickly become a pain.
Well, I guess that FILT is the way to go now.
Edited once by Fusionftw. Last: 4th Jun 2020 -
there's a mod with logic gates, all inputs are just pscn and all outputs are just nscn
