EDUC mk1 (educational computer)

  • zaicev9797
    16th May 2022 Member 1 Permalink



    - 8 bits arch (8bit operands and 8bit RAM address)
    - 3.2Hz speed (19 frames per clock)

    - variable program cycle length (1 clock for NOP operation and up to 4 clocks in currently implemented instructions. 5 clocks length instructions are possible)

    - up to 32 instructions can be implemented

    - one general purpose register (RGA) with abbility to accumualte data from adder and shift/rotate it in any direction and three simple registers (rgb, rgc, rgd)
    - 2 I\O ports could be used to connect other devices (like screen and disk in this save)

     

    I've noticed that there is a lot of computers designed in tpt, but no one is explaining how does it works, what is a structure of a computer. So I'll make my own computer, and later u'll be able to check each part of it with explanation.

     

    Work still in progress.

     

    Changelog:

     

    05-27-2022

     - disk controller and it's data transfering protocol were upgraded and now data transferring is synchronous (disk contoller clock is tuned to allign with computer clock). Now data reading is ~3x faster

     - screen controller and it's data transfering protocol were upgraded and now data transferring is synchronous (screen contoller clock is tuned to allign with computer clock). Now data transferring is ~4x faster and printing program ~2x times smaller.

     

    05-31-2022:
     - updated RAM module to reduce timings

     - small updated to program counter, adder and some other parts to reduce timings

     - CLK was overclocked from 1.7Hz to 3.2Hz (~19 frames per clock) so computer now almost 2x faster

     - "fast nop" was temporary disabled so NOP operation now takes two clocks instead of one

    Edited 4 times by zaicev9797. Last: 31st May 2022
  • zaicev9797
    27th May 2022 Member 1 Permalink

    Update 05-27-2022:

     - disk controller and it's data transfering protocol were upgraded and now data transferring is synchronous (disk contoller clock is tuned to allign with computer clock). Now data reading is ~3x faster

     - screen controller and it's data transfering protocol were upgraded and now data transferring is synchronous (screen contoller clock is tuned to allign with computer clock). Now data transferring is ~4x faster and printing program ~2x times smaller.

  • zaicev9797
    31st May 2022 Member 1 Permalink

    Update 05-31-2022:
     - updated RAM module to reduce timings

     - small updated to program counter, adder and some other parts to reduce timings

     - CLK was overclocked from 1.7Hz to 3.2Hz (~19 frames per clock) so computer now almost 2x faster

     - "fast nop" was temporary disabled so NOP operation now takes two clocks instead of one

    Edited 2 times by zaicev9797. Last: 31st May 2022