Oh nice. Did you found another that tells how a GPU works?

I do see an inconsistency in the Scott CPU (at least as this video portrays it). It appears the RAM data bus is doubling as both a bus to retrieve and set data, however, the data register appears to be one way in their illustration.

I imagine in an actual implementation the RAM data bus register would have a third flag telling it to flood the RAM data bus with its current value, in addition to its flags to change value, and flood the internal cpu bus.

It might also need a second set flag signifying which side of the register to set its value to, but I think it could reasonably get away with just one if it could avoid ever flooding both buses.