brXray3
brXray3
3 / 0
17th Dec 2020
17th Dec 2020
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Comments

  • brXray3
    brXray3
    17th Dec 2020
    sprk* (comment too short)
  • brXray3
    brXray3
    17th Dec 2020
    if you're talking about AND mode in full adder, I saw some adders using lsns and tried to make my own version. In this case, DTEC looks for a bray, gets life 1, and lsns changes the filt's stage, allowing a type of AND gate.
  • brXray3
    brXray3
    17th Dec 2020
    I don't know if it's different. I just used a full adder and some logical processes using the filt.
  • bodester
    bodester
    17th Dec 2020
    nvm silly question
  • bodester
    bodester
    17th Dec 2020
    Awesome, how is this different from using AND mode FILT?