Each address has the possibility of having 28 bits. The addressing unit shifts the "drive" forward (and has a reset button).
filt
memory
fram
electronics
electronic
Comments
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Okay, I fixed the read/write conundrum by putting a PSCN with a DLAY and an NSCN next to the piston. That way it holds the piston there just long enough to read/write. I also implemented the redshifted keepalive. And I designed a bumper made of VOID. Thanks!
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Yeah, you have to reset the read/write pin every time you want to write. And yes, I should design a bumper for the main addressing piston. Yeah, the keepalive thing does get in the way. I kept trying to design a memory module, but then it kept turning to a temperature-based color, so that's a problem. Maybe I will do it red. Thanks for all your help
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It does. I still have to remove the "read" and "write" labels, obviously. There are things to be said though. Since the piston has no bumper on the left, multiple signals on the read pin mess up the read/write head. Also, doesn't the keepalive bit get in the way? I use bit 29 for that. ... Oh, and thanks! Keep tuned for the next model.
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Also, thanks for the feedback! I'm a big admirer of your subframe computer!
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Hmm... Yeah, I guess physical space is a problem. I'll try to fix the 128 and 64 slot on the addressing unit. Perhaps I'll just make it a 128-address memory. But all of the 8-bit read/write functionality works for you, right?
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For some reason I can't get the more significant bits of the address working. Setting the tmps of the address PSTNs to values like 10000 fixes it though. That said, when I want to address the 255th FILT, some of the storage just goes outside simulation bounds and disappears.