Started 6/17/16. Breakthrough design completed 8/10/16. 8/15/16 Published adder designs. 10/2/16 Mk2 version with bit retention completed. 10/7/16 Mk3 complete. 3/2/17 Mk4 complete! 10/8/17 Final release, finally! Description in save.
60hz
subframe
electronic
electronics
adder
math
processing
components
counter
Comments
-
@NoVIcE can't wait for floating-point hardware!! :D And then multi-core 'GPU's
-
Great, they are small AND subframe. If we could make a real small 60 clock cycles computer, it would be very cool.
-
yay! I've been checking this save like everyday
-
Can't wait for moar stuff!
-
10/8/17 Presently caught up in my second co-op workterm. Now with mark2222's decimal multiplier out there, I have finally released this months-due save with demo and description.
-
7/2/17 Demo interface to 3-in-1 adder finished. Working on final presentation.
-
Ah yisssssss some updates
-
6/23/17 4th Generation Mk4 Adder finalized and purged of unnecessary DMND layering. Now in final form factor. :D I/O demonstration underway.
-
6/23/17 Started implementing CONV updates; removing unneeded DMND layering.
-
i've started work on my own subframe FILT logic circuits now! Though they're mostly useless repeating red-shifters :P