Tesla-A8D4 Management Computer

Description:
	The T-A8D4 is a four-bit computer with one tellabyte (256 bytes) of internal memory. All of the A8D4's memory is readable as well as writable. This makes the computer more versatile, but means that programs writing to memory should be written with caution as to not make a program that overwrites itself.
	The A8D4's prime purpose of that of micromanagement. Therefore, the computer has been build with 4-bit input and output ports.

Physical:
	Unlike most computers, the A8D4 does not have a dedicated address or data bus. Instead, it has an "Information Bus", acting as both the data bus and address bus.

Graphical Display:(Optional)
	The graphical display is directly mapped to memory addresses E0 to FF. The display is 32 by 4 pixels in size, with one pixel per bit of memory. A '1' is represented by a black pixel and a '0' is represented by a white pixel.

Pinout:
	The A8D4 has 13 pins for I/O

	Pins:
		1 :INPUT REQUEST
			This pin sends a pulse on the EIP command, meaning that pins 2-5 are open.
		2 :Input bits 0-3
		3 :
		4 :
		5 :
		6 :INPUT AKNOWLEDGE
			Pulsed on the use of the LD a,Input command, meaning that pins 2-5 are closed.
		7 :Output bits 0-3
		8 :
		9 :
		10:
		11:OUTPUT SIGNAL
			Pulsed when the computer sends an output on pins 7-10.
		12:START
			Starts the computer if it is stopped
		13:STOP SIGNAL
			Pulses if the computer stops

Commands:
	Add
		Add a number with register A. The result is stored in A.

	Sub
		Subtract a number from register A. The result is stored in A.

	Inc
		Increment a value.

	JP
		Jump to a point in memory. (Note: When jumping, jump to one byte before the desired address, as the A8D4 increments its Program Counter -before- reading the instruction from the disk)

	Inv
		Invert a flag.

	EIP
		Enable Input. (Note: Once Input is read from, it is reset and the port is closed)

	Stop
		Stop the computer.		

	Opcodes:

	|Decimal
	|  |Hexidecimal
	|  | |Binary
	|  | |    |Effects flag
	|  | |    | |Length in bytes
	|  | |    | | |Time in frames
	|  | |    | | |   |Mneumonic
	|00|0|0000|c|2|065|Add d4
	|01|1|0001|c|1|019|Add b
	|02|2|0010|0|2|106|Sub d4
	|03|3|0011|0|1|059|Sub b
	|04|4|0100|c|1|005|Inc a
	|05|5|0101|c|1|006|Inc hl
	|06|6|0110|c|1|007|Inc b
	|07|7|0111|0|3|122|JP a8
	|08|8|1000|0|3|131|JP c,a8
	|09|9|1001|c|1|018|Inv c
	|10|A|1010|0|1|038|And a,b
	|11|B|1011|0|1|023|JP hl
	|12|C|1100|0|1|007|EIP
	|13|D|1101|0|1|008|LD a,Input
	|14|E|1110|0|1|008|LD Output,a
	|15|F|1111|0|~|62+|Prefix F

	Prefix F:	
	|00|0|0000|0|3|059|LD a,d4
	|01|1|0001|0|4|120|LD hl,d8
	|02|2|0010|0|3|061|LD b,d4
	|03|3|0011|0|2|010|LD a,b
	|04|4|0100|0|2|011|LD b,a
	|05|5|0101|0|2|043|LD a,(hl)
	|06|6|0110|0|2|038|LD (hl),a
	|07|7|0111|0|2|011|LD a,h
	|08|8|1000|0|2|011|LD h,a
	|09|9|1001|0|2|012|LD a,l
	|10|A|1010|0|2|011|LD l,a
	|11|B|1011|0|2|012|LD h,b
	|12|C|1100|0|2|013|LD l,b
	|13|D|1101|0|4|166|LD a,(a8)
	|14|E|1110|0|4|160|LD (a8),a
	|15|F|1111|0|2|~~~|Stop

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