Each line doubles DLAY of previous line, Starting DLAY of each clock respectively at {Line 1; L=1; D(L)} D(1)= 2, 3, 4, 8, 16, 32 - Final Delay of each clock respectively at {Line 9; L=9; D(L)} D(9)= 512, 768, 1024, 2048, 4096, 8192